A Schottky diode is a unipolar device using electrons as carriers, which is characterized by high switching speed and low forward voltage drop. The limitations of Schottky diodes are the relatively low reverse voltage tolerance and the relatively high reverse leakage current. The limitations are related to the Schottky barrier height determined by the metal work function of the metal electrode, and the band gap of the semiconductor, the type and concentration of dopants in the semiconductor layer, and other factors. Recently, a trench-MOS Schottky barrier diode has been disclosed. In the trench-MOS Schottky barrier diode, a trench filled with polysilicon or metallic material is used for pinching the reverse-biased leakage current and thus largely reducing the leakage current of the semiconductor device.
A trench-MOS Schottky barrier diode has been disclosed in U.S. Pat. No. 5,365,102, which is entitled “SCHOTTKY BARRIER RECTIFIER WITH MOS TRENCH”. Please refer to FIGS. 1A˜1F, which schematically illustrate a method of manufacturing a conventional trench MOS Schottky barrier diode.
Firstly, as shown in FIG. 1A, a semiconductor substrate 12 with an epitaxial layer thickness is provided. The substrate 12 has two surfaces 12a and 12b. A heavily-doped (N+ type) cathode region 12c is adjacent to the surface 12a. A lightly-doped (N type) drift region 12d is extended from the heavily-doped (N+ type) cathode region 12c to the surface 12b. A silicon dioxide (SiO2) layer 13 is grown on the substrate 12. A silicon nitride (Si3N4) layer 15 is grown on the silicon dioxide layer 13. The formation of the silicon dioxide layer 13 may reduce the stress that is provided by the silicon nitride layer 15. Moreover, a photoresist layer 17 is formed on the silicon nitride layer 15.
Then, as shown in FIG. 1B, a photolithography and etching process is performed to pattern the photoresist layer 17 and partially remove the silicon nitride layer 15, the silicon dioxide layer 13 and the substrate 12. Consequently, a plurality of discrete mesas 14 are defined in the drift region 12d of the substrate 12. In addition, the etching step defines a plurality of trenches 22. Each trench 22 has a specified depth and a specified width. Then, as shown in FIG. 10, a thermal oxide layer 16 is formed on a sidewall 22a and a bottom 22b of the trench 22. Then, as shown in FIG. 1D, the remaining silicon nitride layer 15 and the remaining silicon dioxide layer 13 are removed. Then, as shown in FIG. 1E, a metallization layer 23 is formed over the resulting structure of FIG. 1D. Then, as shown in FIG. 1F, a metallization process is performed to form another metallization layer (not shown) on the backside surface 12a. After a sintering process is performed, the metallization layer 23 contacted with the discrete mesas 14 are connected with each other to define a single anode electrode layer 23, and a cathode electrode 20 on the backside surface 12a, and a cathode electrode layer 20 is formed on the backside surface 12a. Since the anode electrode layer 23 is contacted with the mesas 14, a so-called Schottky barrier results in a Schottky contact. Meanwhile, the trench MOS Schottky barrier diode is produced.
The trench MOS Schottky barrier rectifier (TMBR) fabricated by the above method has low forward voltage drop. Moreover, since the reverse-biased leakage current is pinched by the trench, the leakage current is reduced when compared with the Schottky diode having no trenches. Generally, for the trench MOS Schottky barrier rectifier to be with a reverse voltage of about 120V, its leakage current of is about several tens of microamps. In practice, the magnitude of the leakage current is also dependent on the chip size. Therefore, the present invention relates to a trench Schottky diode with high reverse voltage and low leakage current.